Analyses

Three solvers, one circuit. The operating point says where the current goes, the response says what the circuit does to a signal, and the run over time says what the waveform looks like — and each refuses by name rather than answering with a plausible fiction.

Every analysis carries the document and revision it was computed for, so a stale result can never render as current. Every one of them is derived from the drawing: nets are rebuilt from the schematic before anything is solved.

Simulation — the DC operating point#

Modified nodal analysis of the circuit as it sits. The matrix is assembled from the derived nets: resistances stamp conductances, sources and zero-impedance elements take a branch row of their own, and the whole thing is solved by Gaussian elimination with partial pivoting.

At DC:

• Capacitors are open and inductors are 0 V branches. A closed switch and a current probe are 0 V branches too.
• An AC source is silent — no volts across an AC voltage source, no amps out of an AC current source — but it is still a wire's worth of copper tying its two nets into one island.
• An ideal transformer is an open: infinite magnetising inductance draws nothing and nothing crosses the core, so both windings read open. That is the truth, not a gap.
• An ideal op-amp is a nullor: it drives whatever output current makes its two inputs match.

Nonlinear parts, settled rather than iterated to#

Diodes, LEDs, Schottkys, zeners and each of a bridge's four cells are the same device to the solver: a junction that is off, forward at a fixed drop, or — a zener — held at its breakdown voltage. Transistors join them: a BJT is off, forward-active with a base-emitter drop of 0.7 V and a collector current of β times the base current (β = 100), or saturated at a collector-emitter drop of 0.2 V; a MOSFET is switch-level, a 500 mΩ channel above a 2.0 V gate threshold and an open below it.

The solver assumes a state for every one of them, solves the linear network, moves whatever the answer contradicts, and repeats. It is deterministic — no Newton convergence roulette — and a network that will not settle refuses rather than reporting the last guess.

What you read#

Measurements holds two tables. Node voltages lists every net that a part touches, by name; the caption adds "· auto reference" when no ground was placed. Components lists every part with its current, its voltage and its power. Clicking a row selects the part on the sheet.

The reference node is picked in a fixed order: a ground symbol first, then a source's − terminal, then the lowest net id. Each electrically separate island gets its own.

Simulation states the same solve in a sentence — "Solved · revision 9 · 6 components · I = 40.9 mA · P = 368 mW" — and adds what is worth knowing about it:

• "· a switch is open"
• "· steady state — capacitors are open at DC; the transient needs time"
• "· no ground placed — voltages read against an automatic reference"

The status bar carries the headline while you work: the source current when there is exactly one source, otherwise the total power.

When it refuses#

Response — the small-signal frequency sweep#

A second solver, and a genuinely different machine: every quantity is a phasor, the matrix is complex, and it is rebuilt once per frequency.

Set from, to and per decade (5, 10, 20 or 50), and pick which net to plot. Frequencies are spaced logarithmically with both endpoints included, capped at 400 points — past that the panel says so rather than passing a coarser curve off as the one you asked for. The default sweep runs 1 Hz to 1 MHz at twenty points per decade. The sweep runs only while its panel is open.

What it models#

• R, L and C are ideal: 1/R, jωC, 1/(jωL). No ESR, no self-resonance.
• A source's DC value sets the operating point; its AC amplitude sets the stimulus. A voltage source with no AC drive is a short to the signal and a current source with none is an open — which is what they physically are.
• Nonlinear parts are linearised about the DC operating point, so the operating point is solved first and its refusal is inherited. A conducting junction becomes r_d = V_T / |I_D| with V_T = 25.852 mV at 300 K; a zener in breakdown becomes its Dynamic R, which is a datasheet number and the whole reason it regulates; a forward-active BJT becomes hybrid-π with g_m = |I_C| / V_T and r_π = β / g_m; a MOSFET stays switch-level.
• The Early effect is not modelled, so r_o is infinite. The result says nothing about clipping, slew, or distortion.

Each linearisation is reported under the plot, by name: "D1 linearised at r_d = 1.29 Ω from 20.0 mA of bias." · "Q1 linearised at g_m = 38.7 mS, r_π = 2.58 kΩ from 1.00 mA of collector current." · "M1 is modelled switch-level at AC — 500 mΩ channel, no transconductance." A part that is simply off says so too, and a bridge says a little more, because a rectifier is a large-signal device and a sweep about a blocking bias sees an open.

Reading the plot#

The Bode plot puts magnitude in decibels and unwrapped phase in degrees on one shared logarithmic axis — decibels labelled left, phase right — because a reader comparing where the gain falls to where the phase turns should not have to move their eye between two boxes. Phase is unwrapped before it is drawn, so a second pole does not make the trace fall off the bottom and reappear at the top.

Decibels are taken against the stimulus amplitude, so 0 dB is unity. Hover for a readout; click the plot to pin a frequency and a table of every phasor at that point appears beside it, each as magnitude and angle — 12.3 mV ∠ −45.0°. Click again to unpin.

Worked, on a first-order low-pass: the magnitude trace is flat at 0 dB, bends at the corner, and falls 20 dB per decade after it. Pin the corner and you should read −3.01 dB with the phase at −45.0°; a decade past it, −20 dB and close to −90°. The two landing together is the check that you are looking at one real pole rather than at something the plot's scaling flattered.

When it refuses#

Transient — the run over time#

The third solver, and the one with a clock. It answers what neither of the others can: how long the capacitor takes to charge, what a rectifier's output looks like, why an inductor spikes when the switch opens.

The method is backward Euler with companion models. At each step a capacitor becomes a conductance C/h in parallel with a source holding last step's voltage, an inductor becomes h/L in parallel with a source holding last step's current, and the same piecewise-linear settler runs as at the operating point. Backward Euler rather than trapezoidal on purpose: trapezoidal is more accurate on a smooth waveform but rings on every discontinuity, and this solver exists for circuits full of diodes that switch. A numerical ring is indistinguishable on screen from a real one. The panel states the method every run: "Backward Euler at 10.0 µs per step. Stable and slightly damped by construction, so a ring you can see is a ring the circuit has."

Set run for and step, and choose which nets to trace; with nothing chosen it traces up to two nets that a capacitor or inductor is attached to, because that is almost always what a run is asking about. A capacitor's Initial V and an inductor's Initial I are where the run starts. A switch's Flips at changes its state mid-run, and the panel notes it: "A switch changes state during this run — the step it lands on is where the waveform turns."

The scope draws every trace on one linear axis in the same units. A long run is bucketed to fit the plot, keeping each bucket's minimum and maximum rather than one sample from it — a dropped extreme is a spike that silently disappears, which on a waveform is the one thing you were looking for. Click to pin an instant and read every part's current and voltage there.

When it refuses#

A step that fails mid-run reports the reason with the instant it happened at, so you can go and look at that instant.

Solver — the worked steps#

The Solver tab explains a solved circuit. Pick a component under Solve for and a quantity — current or voltage — and the panel writes the hand calculation out: series resistances adding, Ohm's law around the loop, the voltage divider, parallel conductances adding, or node-voltage analysis as the general fallback. Its assumptions are printed above the steps, and they are the ones the method actually rests on: ideal DC source and ideal conductors; steady state, so capacitors carry no DC current; inductors are shorts at DC; diodes use the piecewise-linear model, a Vf drop when conducting.

Every result is cross-checked against the operating point before it is shown. Agreement is a chip reading matches the simulation; disagreement reads check against simulation and adds "Step result disagrees with the simulated operating point — trust the simulation." Nothing here is generated prose — the steps are derived from the circuit graph.

If the circuit does not solve, the tab says "The solver explains a solved circuit — fix the refusal first."

Problems#

Problems watches while you draw, independently of any solve, and its tab carries a count. Structural problems are found without solving:

• "R1 has an unconnected terminal — nothing reaches pin 1." — an error, or a warning for a voltage probe.
• "Two components share the reference R1 — rename one so measurements stay unambiguous."
• "No reference node. Add a ground symbol so node voltages read against 0 V — analysis still runs with an automatic reference."

Two more arrive after the operating point is known:

• "R1 dissipates 500 mW — above its 250 mW rating." — when you have given the part a Power rating.
• "D1 carries 21.2 mA — above a typical 20 mA.", or "— add a current-limiting resistor" when there is no resistor in the circuit at all.

Every row is clickable and selects the part it is about.

Next#

• Circuits in your deck — putting a solved circuit on a slide.
• Tutorial: an RC filter from scratch — DC, AC and a corner frequency, end to end.